Conference Articles by Year:


Journal Articles by Year:


Publications

Journal

2016

  • R. K. Nandwana, S. Saxena, A. Elshazly, K. Mayaram, and P. K. Hanumolu, “A fully-integrated low frequency input reference, 1-to-2048 cascaded digital frequency synthesizer using scrambling TDC,” IEEE Trans. Circuits Syst. I. [Link]
  • J. Zhu, R. K. Nandwana, G. Shu, A. Elkholy, S. J. Kim, P. K. Hanumolu, “A 0.0021 mm² 1.82 mW 2.2 GHz PLL using time-based integral control in 65 nm CMOS,” in IEEE J. Solid-State Circuits , vol.PP, no.99, pp.1-13 [Link]
  • T. Anand, K. A. A. Makinwa, P. K. Hanumolu, “A VCO based highly digital temperature sensor with 0.034 °C/mV supply sensitivity,” in IEEE J. Solid-State Circuits , vol. 51, no. 11, pp. 2561-2663, Nov. 2016. [Link]
  • A. Elkholy, S. Saxena, R. K. Nandwana, A. Elshazly, and P. K. Hanumolu, “A 2.0-5.5 GHz wide bandwidth ring-based digital fractional-N PLL with extended range multi-modulus divider,” in IEEE J. Solid-State Circuits, vol. 51, no. 8, pp. 1771-1784, Aug. 2016. [Link]
  • G. Shu, W. S. Choi, S. Saxena, M. Talegaonkar, T. Anand, A. Elkholy, A. Elshazly, and P. K. Hanumolu, “A 4-to-10.5 Gb/s continuous-rate digital clock and data recovery with automatic frequency acquisition,” in IEEE J. Solid-State Circuits, vol. 51, no. 2, pp. 428-439, Feb. 2016. [Link]

2015

  • A. Elkholy, M. Talegaonkar, T. Anand, and P. K. Hanumolu, “Design and analysis of low-power high-frequency robust sub-harmonic injection-locked clock multipliers,” IEEE J. Solid-State Circuits, vol. 50, no. 12, pp. 3160-3174, Dec. 2015. [Link]
  • T. Anand, M. Talegaonkar, A. Elkholy, S. Saxena, A. Elshazly, and P. K. Hanumolu, “A 7 Gb/s embedded clock transceiver for energy proportional links,” IEEE J. Solid-State Circuits, vol. 50, no. 12, pp. 3101-3119, Dec. 2015. [Link]
  • S.-J. Kim, R. K. Nandwana, Q. Khan, R. Pilawa-Podgurski, and P. K. Hanumolu, “A 4-phase 30–70 MHz switching frequency buck converter using a time-based compensator, ” IEEE J. Solid-State Circuits, vol. 50, no. 12, pp. 2814-2824, Dec. 2015. [Link]
  • P. Prabha, S.-J. Kim, K. Reddy, S. Rao, N. Griesert, A. Rao, G. Winter, and P.K. Hanumolu, “A highly digital VCO-based ADC architecture for current sensing applications,” IEEE J. Solid-State Circuits,vol. 50, no. 8, pp. 1785-1795, Aug. 2015. [Link]
  • S.-J. Kim, Q. Khan, M. Talegaonkar, A. Elshazly, A. Rao, N. Griesert, G. Winter, W. McIntyre, and P. K. Hanumolu, “High frequency buck converter design using time-based control techniques,” IEEE J. Solid-State Circuits,vol. 50, no. 4, pp. 990-1001, Apr. 2015. [Link]
  • R. K. Nandwana, T. Anand, S. Saxena, S. –J. Kim, M. Talegaonkar, A. Elkholy, W.-S. Choi, A. Elshazly, and P. K. Hanumolu, “A calibration-free fractional-N ring PLL using hybrid phase/current-mode phase interpolation method,” IEEE J. Solid-State Circuits, vol. 50, no. 4, pp. 882-895, Apr. 2015. [Link]
  • A. Elkholy, T. Anand, W.-S. Choi, A. Elshazly, P. K. Hanumolu, “A 3.7mW low-noise wide-bandwidth 4.5GHz digital fractional-N PLL using time amplifier-based TDC,” IEEE J. Solid-State Circuits, vol. 50, no. 4, pp. 867-881, Apr. 2015. [Link]
  • W.-S. Choi, T. Anand, G. Shu, A. Elshazly, and P. K. Hanumolu, “A burst-mode digital receiver with programmable input jitter filtering for energy proportional links,” IEEE J. Solid-State Circuits, vol. 50, no. 3, pp. 237-248, Mar. 2015. [Link]

2014

  • T. Anand, A. Elshazly, M. Talegaonkar, B. Young, and P. Hanumolu, “A 5Gb/s, 10ns power-on-time, 36μW off-state power, fast power-on transmitter for energy proportional links”, IEEE J. Solid-State Circuits, vol. 49, no 10, pp. 2243-2258, Oct. 2014. [Link]
  • M. Talegaonkar, A. Elshazly, K. Reddy, P. Prabha, T. Anand, and P. K. Hanumolu, “An 8 Gb/s–64 Mb/s, 2.3–4.2 mW/Gb/s burst-mode transmitter in 90 nm CMOS,” IEEE J. Solid-State Circuits, vol. 49, no. 10, pp. 2228-2242, Oct. 2014. [Link]
  • S. Saxena, R. K. Nandwana, and P. K. Hanumolu, “A 5Gb/s energy-efficient voltage-mode transmitter using time-based de-emphasis,” IEEE J. Solid-State Circuits, vol. 49, no. 8, pp. 1827-1836, Aug. 2014.[Link]
  • A. Elshazly, S. Rao, B. Young, and P. Hanumolu, “A noise-shaping time-to-digital converter using switched-ring oscillators – analysis, design, and measurement techniques,” IEEE J. Solid-State Circuits, vol. 49, no. 5, pp. 1184-1197, May 2014. [Link]
  • S. Rao, K. Reddy, B. Young, and P. Hanumolu, “A deterministic digital background calibration technique for VCO-based ADCs,” IEEE J. Solid-State Circuits, vol. 49, no. 4, pp. 950-960, Apr. 2014. [Link]
  • G. Shu, S. Saxena, W. -S. Choi, M. Talegaonkar, A. Elshazly, B. Young, and P. K. Hanumolu, “A reference-less clock and data recovery circuit using phase-rotating phase-locked loop,” IEEE J. Solid-State Circuits, vol. 49, no. 4, pp. 1036-1047, Apr. 2014. [Link]

2013

  • A. Elshazly, R. Inti, B. Young, and P.K. Hanumolu, “Clock multiplication techniques using digital multiplying delay-locked loops,” IEEE J. Solid-State Circuits, vol. 48, no. 6, pp. 1416-1428, June 2013.[Link]
  • R. Zanbaghi, P.K. Hanumolu, and T.S. Fiez, “An 80-dB DR, 7.2-MHzbandwidth single opamp biquad based CT ΔΣ modulator dissipating 13.7-mW,” IEEE J. Solid-State Circuits, vol. 48, no. 2, pp. 487-501, Feb. 2013. [Link]

2012

  • K. Reddy, S. Rao, R. Inti, B. Young, A. Elshazly, M. Talegaonkar, and P.K. Hanumolu, “A 16-mW 78-dB SNDR 10-MHz BW CT ΔΣ ADC using residue-cancelling VCO-based quantizer,” IEEE J. Solid-State Circuits, vol. 47, no. 12, pp. 2916-2927, Dec. 2012. [Link]
  • B. Drost, M. Talegaonkar, and P.K. Hanumolu, “Analog filter design using ring oscillator integrators,” IEEE J. Solid-State Circuits, vol. 47, no. 12, pp. 3120-3129, Dec. 2012. [Link]
  • N. Sasidhar, D. Gubbins, P.K. Hanumolu, and U.-K. Moon, “Rail-to-rail input pipelined ADC incorporating multistage signal mapping,” IEEE Trans. Circuits Syst. II, vol. 59, no. 9, pp. 558-562, Sept. 2012. [Link]
  • S. Zaliasl, S. Saxena, P.K. Hanumolu, K. Mayaram, and T.S. Fiez, “A 12.5-bit 4 MHz 13.8 mW MASH ΔΣ modulator with multirated VCO-based ADC,” IEEE Trans. Circuits Syst. I, vol. 59, no. 8, pp. 1604-1613, Aug. 2012. [Link]

2011

  • W. Yin, R. Inti, A. Elshazly, M. Talegaonkar, B. Young, and P.K. Hanumolu, “A TDC-less 7 mW 2.5 Gb/s digital CDR with linear loop dynamics and offset-free data recovery,” IEEE J. Solid-State Circuits, vol. 46, no. 12, pp. 3163-3173, Dec. 2011. [Link]
  • R. Inti, W. Yin, A. Elshazly, N. Sasidhar, and P.K. Hanumolu, “A 0.5-to-2.5 Gb/s reference-less half-rate digital CDR with unlimited frequency acquisition range and improved input duty-cycle error tolerance,” IEEE J. Solid-State Circuits, vol. 46, no. 12, pp. 3150-3162, Dec. 2011. [Link]
  • S. Rao, Q. Khan, S. Bang, D. Swank, A. Rao, W. McIntyre, and P.K. Hanumolu, “A 1.2-A buck-boost LED driver with on-chip error averaged senseFET-based current sensing technique,” IEEE J. Solid-State Circuits, vol. 46, no. 12, pp. 2772-2783, Dec. 2011. [Link]
  • A. Elshazly, R. Inti, W. Yin, B. Young, and P.K. Hanumolu, “A 0.4-to-3GHz digital PLL with PVT insensitive supply noise cancellation using deterministic background calibration,” IEEE J. Solid-State Circuits, vol. 46, no. 12, pp. 2759-2771, Dec. 2011. [Link]
  • W. Yin, R. Inti, A. Elshazly, B. Young, and P.K. Hanumolu, “A 0.7-to-3.5 GHz 0.6-to-2.8 mW highly digital phase-locked loop with bandwidth tracking,” IEEE J. Solid-State Circuits, vol. 46, no. 8, pp. 1870-1880, Aug. 2011. [Link]
  • Y. Wang, P.K. Hanumolu, and G.C. Temes, “Design techniques for wideband discrete-time delta-sigma ADCs with extra loop delay,” IEEE Trans. Circuits Syst. I, vol. 58, no. 7, pp. 1518-1530, July 2011.[Link]
  • I. Vytyaz, P.K. Hanumolu, U.-K. Moon, and K. Mayaram, “Design-oriented analysis of circuits with equality constraints,” IEEE Trans. Circuits Syst. I, vol. 58, no. 5, pp. 1089-1098, May 2011. [Link]

2010

  • A. Arakali, S. Gondi, and P.K. Hanumolu, “Analysis and design techniques for supply-noise mitigation in phase-locked loops,” IEEE Trans. Circuits Syst. I, vol. 57, no. 11, pp. 2880-2889, Nov. 2010.[Link]
  • D. Gubbins, B. Lee, P.K. Hanumolu, and U.-K. Moon, “Continuous-time input pipeline ADCs,” IEEE J. Solid-State Circuits, vol. 45, no. 8, pp. 1456-1468, Aug. 2010. [Link]
  • B. Young, and P.K. Hanumolu, “Phase-locked loop based Δ-Σ ADC,” Electronic Letters, vol. 46, no. 6, pp. 403-404, Mar. 2010. [Link]

2009

  • A. Agrawal, A. Liu, P.K. Hanumolu, and G.-Y. Wei, “An 8×5 Gb/s parallel receiver with collaborative timing recovery,” IEEE J. Solid-State Circuits, vol. 44, no. 11, pp. 3120-3130, Nov. 2009. [Link]
  • N. Sasidhar, Y.-J. Kook, S. Takeuchi, K. Hamashita, K. Takasuka, P.K. Hanumolu, and U.-K. Moon, “A low power pipelined ADC using capacitor and opamp sharing technique with a scheme to cancel the effect of signal dependent kickback,” IEEE J. Solid-State Circuits, vol. 44, no. 9, pp. 2392-2401, Sept. 2009. [Link]
  • M.G. Kim, P.K. Hanumolu, and U.-K. Moon, “A 10 MS/s 11-bit 0.19 mm2 algorithmic ADC with improved clocking scheme,” IEEE J. Solid-State Circuits, vol. 44, no. 9, pp. 2348-2355, Sept. 2009. [Link]
  • A. Arakali, S. Gondi, and P.K. Hanumolu, “Low-power supply-regulation techniques for ring oscillators in phase-locked loops using a split-tuned architecture,” IEEE J. Solid-State Circuits, vol. 44, no. 8, pp. 2169-2181, Aug. 2009. [Link]
  • N. Sasidhar, R. Inti, and P.K. Hanumolu, “Low-noise self-referenced cmos oscillator,” Electronics Letters, vol. 45, no. 18, pp. 920-921, Aug. 2009. [Link]
  • V. Kratyuk, P.K. Hanumolu, K. Ok, U.-K. Moon, and K. Mayaram, “A digital PLL with a stochastic time-to-digital converter,” IEEE Trans. Circuits Syst. I, vol. 56, no. 8, pp. 1612-1621, Aug. 2009. [Link]
  • I. Vytyaz, D.C. Lee, P.K. Hanumolu, U.-K. Moon, and K. Mayaram, “Automated design and optimization of low-noise oscillators,” IEEE Trans. Computer-Aided Design of Integr. Circuits Syst., vol. 28, no. 5, pp. 609-622, May 2009. [Link]
  • T. Wu, P.K. Hanumolu, K. Mayaram, and U.-K. Moon, “Method for a constant loop bandwidth in LC-VCO PLL frequency synthesizers,” IEEE J. Solid-State Circuits, vol. 44, no. 2, pp. 427-435, Feb. 2009. [Link]

2008

  • I. Vytyaz, D.C. Lee, P.K. Hanumolu, U.-K. Moon, and K. Mayaram, “Sensitivity analysis for oscillators,” IEEE Trans. Computer-Aided Design of Integr. Circuits Syst., vol. 27, no. 9, pp. 1521-1534, Sept. 2008. [Link]
  • M.G. Kim, G.-C. Ahn, P.K. Hanumolu, S.-H. Lee, S.-H. Kim, S.-B. You, J.-W. Kim, G.C. Temes, and U.-K. Moon, “A 0.9V 92dB double-sampled switched-RC delta-sigma audio ADC,” IEEE J. Solid-State Circuits, vol. 43, no. 5, pp. 1195-1206, May 2008. [Link]
  • P.K. Hanumolu, G.-Y. Wei, and U.-K. Moon, “A wide-tracking range clock and data recovery circuit,” IEEE J. Solid-State Circuits, vol. 43, no. 2, pp. 425-439, Feb. 2008. [Link]
  • P.K. Hanumolu, V. Kratyuk, G.-Y. Wei, and U.-K. Moon, “A sub-picosecond resolution 0.5-1.5 GHz digital-to-phase converter,” IEEE J. Solid-State Circuits, vol. 43, no. 2, pp. 414-424, Feb. 2008. [Link]

2007

  • P. Kurahashi, P.K. Hanumolu, G.C. Temes, and U.-K. Moon, “Design of low-voltage highly linear switched-R-MOSFET-C filters,” IEEE J. Solid-State Circuits, vol. 42, no. 8, pp. 1699-1709, Aug. 2007. [Link]
  • V. Kratyuk, P.K. Hanumolu, U.-K. Moon, and K. Mayaram, “A design procedure for all-digital phase-locked loops based on a charge-pump phase-locked-loop analogy,” IEEE Trans. Circuits Syst. II, vol. 54, no. 3, pp. 247-251, Mar. 2007. [Link]
  • V. Kratyuk, P.K. Hanumolu, U.-K. Moon, and K. Mayaram, “Frequency detector for fast frequency lock of digital PLLs,” Electronics Letters, vol. 43, no. 1, pp. 13-14, Jan. 2007. [Link]

2006

  • M. Brownlee, P.K. Hanumolu, K. Mayaram, and U.-K. Moon, “A 0.5-GHz to 2.5-GHz PLL with fully differential supply regulated tuning,” IEEE J. Solid-State Circuits, vol. 41, no. 12, pp. 2720-2728, Dec. 2006. [Link]

2005

  • G. Vemulapalli, P.K. Hanumolu, Y.-J. Kook, and U.-K. Moon, “A 0.8-V accurately tuned linear continuous-time filter,” IEEE J. Solid-State Circuits, vol. 40, no. 9, pp. 1972-1977, Sept. 2005. [Link]

2004

  • P.K. Hanumolu, M. Brownlee, K. Mayaram, and U.-K. Moon, “Analysis of charge-pump phase-locked loops,” IEEE Trans. Circuits Syst. I, vol. 51, no. 9, pp. 1665-1674, Sept. 2004. [Link]

Conference

2016

  • J. Zhu, R. K. Nandwana, G. Shu, A. Elkholy, S. J. Kim and P. K. Hanumolu, “19.8 A 0.0021mm2 1.82mW 2.2GHz PLL using time-based integral control in 65nm CMOS,” 2016 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, 2016, pp. 338-340. [Link]
  • A. Elkholy, A. Elmallah, M. Elzeftawi, K. Chang and P. K. Hanumolu, “10.6 A 6.75-to-8.25GHz, 250fsrms-integrated-jitter 3.25mW rapid on/off PVT-insensitive fractional-N injection-locked clock multiplier in 65nm CMOS,” 2016 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, 2016, pp. 192-193. [Link]
  • G. Shu et al., “23.1 A 16Mb/s-to-8Gb/s 14.1-to-5.9pJ/b source synchronous transceiver using DVFS and rapid on/off in 65nm CMOS,” 2016 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, 2016, pp. 398-399. [Link]

2015

  • A. Elkholy, S. Saxena, R. K. Nandwana, A. Elshazly, and P. K. Hanumolu, “A 4mW wide bandwidth ring-rased fractional-N DPLL with 1.9psrms integrated jitter,” in Proc. IEEE Custom Integr. Circuits Conf. (CICC), Sep. 2015.
  • S. Saxena, G. Shu, R. K. Nandwana, M. Talegaonkar, A. Elkholy, T. Anand, S. -J. Kim, W.–S. Choi, and P. K. Hanumolu, “A 2.8mW/Gb/s 14Gb/s serial link transceiver in 65nm CMOS,” in IEEE Symp. VLSI Circuits, Jun. 2015. [Link]
  • T. Anand, K.A.A. Makinwa, P. K. Hanumolu , “A self-referenced VCO-based temperature sensor with 0.034°C/mV supply sensitivity in 65nm CMOS,” in IEEE Symp. VLSI Circuits, Jun. 2015. [Link]
  • A. Elkholy, M. Talegaonkar, T. Anand, P. K. Hanumolu, “A 6.75-8.25GHz 2.25mW 190fsrms Integrated-Jitter PVT-insensitive Injection-Locked Clock Multiplier Using All-Digital Continuous Frequency Tracking Loop in 65nm CMOS”, in IEEE ISSCC Dig. Tech. Papers, Feb. 2015. [Link]
  • S.-J. Kim, R. K. Nandwana, Q. Khan, R. Pilawa, P. K. Hanumolu, “A 1.8V 30-to-70MHz 87% Peak-Efficiency 0.32mm2 4-Phase Time-Based Buck Converter Consuming 3µA/MHz Quiescent Current in 65nm CMOS”, in IEEE ISSCC Dig. Tech. Papers, Feb. 2015. [Link]
  • W.-S. Choi, G. Shu, M. Talegaonkar, Y. Liu, D. Wei, L. Benini and P. Hanumolu, “A 0.45-to-0.7V 1-to-6Gb/s 0.29-to-0.58pJ/b source-synchronous transceiver using automatic phase calibration in 65nm CMOS”, in IEEE ISSCC Dig. Tech. Papers, Feb. 2015. [Link]
  • T. Anand, M. Talegaonkar, A. Elkholy, S. Saxena, A. Elshazly, and P. Hanumolu, “A 7Gb/s rapid on/off embedded clock serial link transceiver with 20ns power-on time, 740μW off-state power for energy proportional links in 65nm CMOS”, in IEEE ISSCC Dig. Tech. Papers, Feb. 2015. [Link]

2014

  • P. Prabha, S. –J. Kim, K. Reddy, S. Rao, N. Griesert, A. Rao, G. Winter, and P. K. Hanumolu, “A VCO-based current-to-digital converter for sensor applications,” in IEEE Custom Int. Circuits Conf., Sep. 2014. [Link]
  • Q. Khan, S. Kim, M. Talegaonkar, A. Elshazly, A. Rao, N. Griesert, G. Winter, W. McIntyre, and P. Hanumolu, “A 10-25MHz, 600mA buck converter using time-based PID compensator with 2μA/MHz quiescent current, 94% peak efficiency, and 1MHz BW” in IEEE Symp. VLSI Circuits, Jun. 2014. [Link]
  • R. Nandwana, T. Anand, S. Saxena, S. Kim, M. Talegaonkar, A. Elkholy, W. Choi, A. Elshazly, and P. Hanumolu, “4.25GHz-4.75GHz calibration-free fractional-N ring PLL using hybrid phase/current-mode phase interpolator with 13.2dB phase noise improvement,” in IEEE Symp. VLSI Circuits, Jun. 2014. [Link]
  • B. Young, K. Reddy, S. Rao, A. Elshazly, T. Anand, and P. Hanumolu, “A 75dB DR 50MHz BW 3rd order CT-ΔΣ modulator using VCO-based integrators,” in IEEE Symp. VLSI Circuits, Jun. 2014. [Link]
  • M. Talegaonkar, T. Anand, A. Elkholy, A. Elshazly, R. Nandwana, S. Saxena, B. Young, W. Choi, P. Hanumolu, “A 4.4-5.4GHz digital fractional-N PLL using ΔΣ frequency-to-digital converter,” in IEEE Symp. VLSI Circuits, Jun. 2014. [Link]
  • A. Elkholy, T. Anand, W. Choi, A. Elshazly, and P. Hanumolu, “A 3.7mW 3MHz bandwidth 4.5GHz digital fractional-N PLL with-106dBc/Hz in-band noise using time amplifier based TDC,” in IEEE Symp. VLSI Circuits, Jun. 2014. [Link]
  • A. Elkholy, A. Elshazly, S. Saxena, G. Shu, and P. Hanumolu, “A 20-to-1000MHz ±14ps peak-to-peak jitter reconfigurable multi-output all-digital clock generator using open-loop fractional dividers in 65nm CMOS,” in ISSCC Digest of Technical Papers, Feb. 2014. [Link]
  • G. Shu, W. Choi, S. Saxena, T. Anand, A. Elshazly, and P. Hanumolu, “A 4-to-10.5Gb/s 2.2mW/Gb/s continuous-rate digital CDR with automatic frequency acquisition in 65nm CMOS,” in ISSCC Digest of Technical Papers, Feb. 2014. [Link]

2013

  • S. Saxena, R. Nandwana, P. Hanumolu, “A 5 Gb/s 3.2 mW/Gb/s 28 dB loss-compensating pulse-width modulated voltage-mode transmitter,” in IEEE Custom Int. Circuits Conf., Sep. 2013. [Link]
  • W. Choi, T. Anand, G. Shu, and P. Hanumolu, “A fast power-on 2.2Gb/s burst-mode digital CDR with programmable input jitter filtering,” in IEEE Symp. VLSI Circuits, Jun. 2013. [Link]
  • G. Shu, S. Saxena, W. Choi, M. Talegaonkar, R. Inti, A. Elshazly, B. Young, and P. Hanumolu, “A 5Gb/s 2.6mW/Gb/s reference-less half-rate PRPLL-based digital CDR,” in IEEE Symp. VLSI Circuits, Jun. 2013. [Link]
  • S. Rao, K. Reddy, B. Young, and P. Hanumolu, “A 4.1mW, 12-bit ENOB, 5MHz BW, VCO-based ADC with on-Chip deterministic digital background calibration in 90nm CMOS,” in IEEE Symp. VLSI Circuits, Jun. 2013. [Link]
  • R. Nandwana, S. Saxena, A. Elshazly, K. Mayaram, and P. Hanumolu, “A 2.5GHz 5.4mW 1-to-2048 digital clock multiplier using a scrambling TDC,” in IEEE Symp. VLSI Circuits, Jun. 2013. [Link]
  • T. Anand, M. Talegaonkar, A. Elshazly, B. Young, and P. Hanumolu, “A 2.5GHz, 2.2mW/25µW On/Off-state power, 2psrms long-term jitter, digital clock multiplier with 3 reference cycles power-on time,” in ISSCC Digest of Technical Papers, Feb. 2013. [Link]

2012

  • A. Elshazly, R. Inti, M. Talegaonkar, and P.K. Hanumolu, “A 1.5GHz 1.35mW -112dBc/Hz in-band noise digital phase-locked loop with 50fs/mV supply-noise sensitivity,” in Proc. Symposium on VLSI Circuits (VLSIC), June 2012, pp. 188-189. [Link]
  • Q. Khan, A. Elshazly, S. Rao, R. Inti, and P.K. Hanumolu, “A 900mA 93% efficient 50µA quiescent current fixed frequency hysteretic buck converter using a highly digital hybrid voltage- and current-mode control,” in Proc. Symposium on VLSI Circuits (VLSIC), June 2012, pp. 182-183. [Link]
  • T. Tong, W. Yu, P.K. Hanumolu, and G.C. Temes, “Calibration technique for SAR analog-to-digital converters,” in IEEE Intl. Symp. on Circuits and Systems, May 2012, pp. 2993-2996. [Link]
  • A. Elshazly, S. Rao, B. Young, and P.K. Hanumolu, “A 13b 315fsrms2mW 500MS/s 1MHz bandwidth highly digital time-to-digital converter using switched ring oscillators,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2012, pp. 464-466. [Link]
  • B. Drost, M. Talegaonkar, and P.K. Hanumolu, “A 0.55V 61dB-SNR 67dB-SFDR 7MHz 4th-order Butterworth filter using ring-oscillator-based integrators in 90nm CMOS,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2012, pp. 360-362. [Link]
  • A. Elshazly, R. Inti, B. Young, and P.K. Hanumolu, “A 1.5GHz 890μW digital MDLL with 400fsrms integrated jitter, -55.6dBc reference spur and 20fs/mV supply-noise sensitivity using 1b TDC,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2012, pp. 242-244. [Link]
  • K. Reddy, S. Rao, R. Inti, B. Young, A. Elshazly, M. Talegaonkar, and P.K. Hanumolu, “A 16mW 78dB-SNDR 10MHz-BW CT-ΔΣ ADC using residue-cancelling VCO-based quantizer,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2012, pp. 152-154. [Link]

2011

  • A. Agrawal, P.K. Hanumolu, and G.-Y. Wei, “Area efficient phase calibration of a 1.6 GHz multiphase DLL,” in IEEE Custom Integrated Circuits Conference (CICC), Sept. 2011, pp. 1-4. [Link]
  • B. Yang, B. Drost, S. Rao, and P.K. Hanumolu, “A high-PSR LDO using a feedforward supply-noise cancellation technique,” in IEEE Custom Integrated Circuits Conference (CICC), Sept. 2011, pp. 1-4. [Link]
  • S. Lee, J. Chae, M. Aniya, S. Takeuchi, K. Hamashita, P.K. Hanumolu, and G.C. Temes, “A double-sampled low-distortion cascade ΔΣ modulator with an adder/integrator for WLAN application,” in IEEE Custom Integrated Circuits Conference (CICC), Sept. 2011, pp. 1-4.[Link]
  • M. Talegaonkar, R. Inti, and P.K. Hanumolu, “Digital clock and data recovery circuit design: Challenges and tradeoffs,” in IEEE Custom Integrated Circuits Conference (CICC), Sept. 2011, pp. 1-8. [Link]
  • S. Zaliasl, S. Saxena, P.K. Hanumolu, K. Mayaram, and T.S. Fiez, “A 77dB SNDR, 4MHz MASH ΔΣ modulator with a second-stage multi-rate VCO-based quantizer,” in IEEE Custom Integrated Circuits Conference (CICC), Sept. 2011, pp. 1-4. [Link]
  • Q. Khan, S. Rao, D. Swank, A. Rao, W. McIntyre, S. Bang, and P.K. Hanumolu, “A 3.3V 500mA digital Buck-Boost converter with 92% peak efficiency using constant ON/OFF time delta-sigma fractional-N control,” in Proc. IEEE Euro. Solid-State Circuits Conference (ESSCIRC), Sept. 2011, pp. 439-442. [Link]
  • S. Rao, B. Young, A. Elshazly, W. Yin, N. Sasidhar, and P.K. Hanumolu, “A 71dB SFDR open loop VCO-based ADC using 2-level PWM modulation,” in Proc. Symposium on VLSI Circuits (VLSIC), June 2011, pp. 270-271. [Link]
  • W. Yin, R. Inti, A. Elshazly, and P.K. Hanumolu, “A TDC-less 7mW 2.5Gb/s digital CDR with linear loop dynamics and offset-free data recovery,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2011, pp. 440-442.[Link]
  • R. Inti, W. Yin, A. Elshazly, N. Sasidhar, and P.K. Hanumolu, “A 0.5-to-2.5Gb/s reference-less half-rate digital CDR with unlimited frequency acquisition range and improved input duty-cycle error tolerance,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2011, pp. 438-450.[Link]
  • S. Rao, Q. Khan, S. Bang, D. Swank, A. Rao, W. McIntyre, and P.K. Hanumolu, “A 1.2A buck-boost LED driver with 13% efficiency improvement using error-averaged SenseFET-based current sensing,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2011, pp. 238-240. [Link]
  • R. Inti, A. Elshazly, B. Young, W. Yin, M. Kossel, T. Toifl, and P.K. Hanumolu, “A highly digital 0.5-to-4Gb/s 1.9mW/Gb/s serial-link transceiver using current-recycling in 90nm CMOS,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2011, pp. 152-154. [Link]
  • A. Elshazly, R. Inti, W. Yin, B. Young, and P.K. Hanumolu, “A 0.4-to-3GHz digital PLL with supply-noise cancellation using deterministic background calibration,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2011, pp. 92-94. [Link]

2010

  • W. Yin, R. Inti, and P.K. Hanumolu, “A 1.6mW 1.6ps-rms-jitter 2.5GHz digital PLL with 0.7-to-3.5GHz frequency range in 90nm CMOS,” in IEEE Custom Integrated Circuits Conference (CICC), Sept. 2010, pp. 1-4. [Link]
  • B. Young, S. Kwon, A. Elshazly, and P.K. Hanumolu, “A 2.4ps resolution 2.1mW second-order noise-shaped time-to-digital converter with 3.2ns range in 1MHz bandwidth,” in IEEE Custom Integrated Circuits Conference (CICC), Sept. 2010, pp. 1-4. [Link]
  • S. Bang, D. Swank, A. Rao, W. McIntyre, Q. Khan, and P.K. Hanumolu, “A 1.2A 2MHz tri-mode Buck-Boost LED driver with feed-forward duty cycle correction,” in IEEE Custom Integrated Circuits Conference (CICC), Sept. 2010, pp. 1-4. [Link]
  • J. Chae, S. Lee, M. Aniya, S. Takeuchi, K. Hamashita, P.K. Hanumolu, and G.C. Temes, “A 63 dB 16 mW 20 MHz BW double-sampled ΔΣ analog-to-digital converter with an embedded-adder quantizer,” in IEEE Custom Integrated Circuits Conference (CICC), Sept. 2010, pp. 1-4. [Link]

2009

  • S. Weaver, B. Hershberg, P.K. Hanumolu, and U.-K. Moon, “A multiplexer-based digital passive linear counter (PLINCO),” in Proc. IEEE Intl. Conf. on Electronics, Circuits and Systems (ICECS), Dec. 2009, pp. 607-610. [Link]
  • D. Gubbins, S. Kwon, B. Lee, P.K. Hanumolu, and U.-K. Moon, “A continuous-time input pipeline ADC with inherent anti-alias filtering,” in Proc. IEEE Custom Integrated Circuits Conference (CICC), Sept. 2009, pp. 275-278. [Link]
  • S. Kwon, P.K. Hanumolu, S.-H. Kim, S.-N. Lee, S.-B. You, H.-J. Park, J.-W. Kim, and U.-K. Moon, “An 11mW 100MHz 16X-OSR 64dB-SNDR hybrid CT/DT ΔΣ ADC with relaxed DEM timing,” in Proc. IEEE Custom Integrated Circuits Conference (CICC), Sept. 2009, pp. 171-174.[Link]
  • O. Rajaee, T. Musah, S. Takeuchi, M. Aniya, K. Hamashita, P.K. Hanumolu, and U.-K. Moon, “A 79dB 80 MHz 8X-OSR hybrid delta-sigma/pipeline ADC,” in Proc. Symposium on VLSI Circuits (VLSIC), June 2009, pp. 74-75. [Link]

2008

  • M.G. Kim, V. Kratyuk, P.K. Hanumolu, G.-C. Ahn, S. Kwon, and U.-K. Moon, “An 8mW 10b 50MS/s pipelined ADC using 25dB opamp,” in Proc. IEEE Asian Solid-State Circuits Conference (A-SSCC), Nov. 2008, pp. 49-52. [Link]
  • A. Arakali, N. Talebbeydokthi, S. Gondi, and P.K. Hanumolu, “Supply-noise mitigation techniques in phase-locked loops,” in Proc. IEEE Euro. Solid-State Circuits Conference (ESSCIRC), Sept. 2008, pp. 374-377. [Link]
  • P. Kurahashi, P.K. Hanumolu, and U.-K. Moon, “A 1V downconversion filter using duty-cycle controlled bandwidth tuning,” in Proc. IEEE Custom Integrated Circuits Conference (CICC), Sept. 2008, pp. 707-710. [Link]
  • I. Vytyaz, J. Carnes, T. Wu, P.K. Hanumolu, U.-K. Moon, and K. Mayaram, “Noise tolerant oscillator design using perturbation projection vector analysis,” in Proc. IEEE Custom Integrated Circuits Conference (CICC), Sept. 2008, pp. 695-698. [Link]
  • A. Agrawal, P.K. Hanumolu, and G.-Y. Wei, “A 8x—5 Gb/s source-synchronous receiver with clock generator phase error correction,” in Proc. IEEE Custom Integrated Circuits Conference (CICC), Sept. 2008, pp. 459-462. [Link]
  • A. Arakali, S. Gondi, and P.K. Hanumolu, “A 0.5-to-2.5GHz supply-regulated PLL with noise sensitivity of -28dB,” in Proc. IEEE Custom Integrated Circuits Conference (CICC), Sept. 2008, pp. 443-446.[Link]
  • D. Gubbins, B. Lee, P.K. Hanumolu, and U.-K. Moon, “A continuous-time input pipeline ADC,” in Proc. IEEE Custom Integrated Circuits Conference (CICC), Sept. 2008, pp. 169-172. [Link]
  • I. Vytyaz, P.K. Hanumolu, U.-K. Moon, and K. Mayaram, “Periodic Steady-State Analysis Augmented with Design Equality Constraints,” in Proc. Design, Automation and Test in Europe (DATE), March 2008, pp. 312-317. [Link]
  • A. Agrawal, P.K. Hanumolu, and G.-Y. Wei, “An 8x—3.2Gb/s Parallel Receiver with Collaborative Timing Recovery,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2008, pp. 468-628. [Link]

2007

  • J. Carnes, I. Vytyaz, P.K. Hanumolu, K. Mayaram, and U.-K. Moon, “Design and Analysis of Noise Tolerant Ring Oscillators Using Maneatis Delay Cells,” in Proc. IEEE Intl. Conf. on Electronics, Circuits and Systems (ICECS), Dec. 2007, pp. 494-497. [Link]
  • N. Sasidhar, Y.-J. Kook, S. Takeuchi, K. Hamashita, K. Takasuka, P.K. Hanumolu, and U.-K. Moon, “A 1.8V 36-mW 11-bit 80MS/s pipelined ADC using capacitor and opamp sharing,” in Proc. IEEE Asian Solid-State Circuits Conference (A-SSCC), Nov. 2007, pp. 240-243. [Link]
  • I. Vytyaz, D.C. Lee, P.K. Hanumolu, U.-K. Moon, and K. Mayaram, “Sensitivity analysis for oscillators,” in Proc. IEEE/ACM Intl. Conf. on Computer-Aided Design (ICCAD), Nov. 2007, pp. 458-463. [Link]
  • T. Wu, P.K. Hanumolu, K. Mayaram, and U.-K. Moon, “A 4.2 GHz PLL frequency synthesizer with an adaptively tuned coarse loop,” in Proc. IEEE Custom Integrated Circuits Conference (CICC), Sept. 2007, pp. 547-550. [Link]
  • P.K. Hanumolu, G.-Y. Wei, U.-K. Moon, and K. Mayaram, “Digitally-enhanced phase-locking circuits,” in Proc. IEEE Custom Integrated Circuits Conference (CICC), Sept. 2007, pp. 361-368. [Link]
  • M. Brownlee, P.K. Hanumolu, and U.-K. Moon, “A 3.2Gb/s oversampling CDR with improved jitter tolerance,” in Proc. IEEE Custom Integrated Circuits Conference (CICC), Sept. 2007, pp. 353-356. [Link]
  • G.-C. Ahn, M.G. Kim, P.K. Hanumolu, and U.-K. Moon, “A 1V 10b 30MSPS switched-RC pipelined ADC,” in Proc. IEEE Custom Integrated Circuits Conference (CICC), Sept. 2007, pp. 325-328. [Link]
  • V. Kratyuk, P.K. Hanumolu, K. Mayaram, and U.-K. Moon, “A 0.6GHz to 2GHz digital PLL with wide tracking range,” in Proc. IEEE Custom Integrated Circuits Conference (CICC), Sept. 2007, pp. 305-308.[Link]

2006

  • P. Kurahashi, P.K. Hanumolu, G. Temes, and U.-K. Moon, “A 0.6V highly linear switched-R-MOSFET-C filter,” in Proc. IEEE Custom Integrated Circuits Conference (CICC), Sept. 2006, pp. 833-836.[Link]
  • P.K. Hanumolu, M.G. Kim, G.-Y. Wei, and U.-K. Moon, “A 1.6Gbps digital clock and data recovery circuit,” in Proc. IEEE Custom Integrated Circuits Conference (CICC), Sept. 2006, pp. 603-606.[Link]
  • G.-C. Ahn, P.K. Hanumolu, M. Kim, S. Takeuchi, T. Sugimoto, K. Hamashita, K. Takasuka, G. Temes, and U.-K. Moon, “A 12b 10MS/s Pipelined ADC using reference scaling,” in Proc. Symposium on VLSI Circuits (VLSIC), June 2006, pp. 220-221. [Link]
  • M.G. Kim, G.-C. Ahn, P.K. Hanumolu, S.-H. Lee, S.-H. Kim, S.-B. You, J.-W. Kim, G.C. Temes, and U.-K. Moon, “A 0.9V 92dB double-sampled switched-RC SD audio ADC,” in Proc. Symposium on VLSI Circuits (VLSIC), June 2006, pp. 160-161. [Link]
  • P.K. Hanumolu, V. Kratyuk, G.-Y. Wei, and U.-K. Moon, “A Sub-picosecond resolution 0.5-1.5GHz digital-to-phase converter,” in Proc. Symposium on VLSI Circuits (VLSIC), June 2006, pp. 75-76. [Link]
  • P.K. Hanumolu, G.-Y. Wei, and U.-K. Moon, “A wide tracking range 0.2-4Gbps clock and data recovery circuit,” in Proc. Symposium on VLSI Circuits (VLSIC), June 2006, pp. 71-72. [Link]
  • M.G. Kim, P.K. Hanumolu, and U.-K. Moon, “A 10MS/s 11-b 0.19mm2algorithmic ADC with improved clocking,” in Proc. Symposium on VLSI Circuits (VLSIC), June 2006, pp. 49-50. [Link]
  • V. Kratyuk, P.K. Hanumolu, K. Ok, K. Mayaram, and U.-K. Moon, “A digital PLL with a stochastic time-to-digital converter,” in Proc. Symposium on VLSI Circuits (VLSIC), June 2006, pp. 31-32. [Link]
  • N. Talebbeydokhti, P.K. Hanumolu, P. Kurahashi, and U.-K. Moon, “Constant transconductance bias circuit with an on-chip resistor,” in IEEE Intl. Symp. on Circuits and Systems (ISCAS), May 2006, pp. 2857-2860. [Link]
  • M. Brownlee, P.K. Hanumolu, K. Mayaram, and U.-K. Moon, “A 0.5 to 2.5GHz PLL with fully differential supply-regulated tuning,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2006, pp. 2412-2421. [Link]

2005

  • T. Wu, P.K. Hanumolu, U.-K. Moon, and K. Mayaram, “An FMDLL based dual-loop frequency synthesizer for 5 GHz WLAN applications,” in IEEE Intl. Symp. on Circuits and Systems (ISCAS), May 2005, vol. 4, pp. 3986-3989. [Link]
  • V. Kratyuk, P.K. Hanumolu, U.-K. Moon, and K. Mayaram, “A low spur fractional-N frequency synthesizer architecture,” in IEEE Intl. Symp. on Circuits and Systems(ISCAS), May 2005, vol. 3, pp. 2807-2810.[Link]

2004

  • M. Brownlee, P.K. Hanumolu, U.-K. Moon, and K. Mayaram, “The effect of power supply noise on ring oscillator phase noise,” in Proc. IEEE Northeast Workshop on Circuits and Systems (NEWCAS), June 2004, pp. 225-228. [Link]
  • P.K. Hanumolu, B. Casper, R. Mooney, G.-Y. Wei, and U.-K. Moon, “Jitter in high-speed serial and parallel links,” in IEEE Intl. Symp. on Circuits and Systems (ISCAS), May 2004, vol. 4, pp. 425-428. [Link]
  • G. Vemulapalli, P.K. Hanumolu, and U.-K. Moon, “A 0.8V accurately-tuned continuous-time filter,” in Proc. IEEE Custom Integrated Circuits Conference (CICC), Oct. 2004, pp. 45-48. [Link]