Contents
Journal
2018
 A. Elkholy, A. Elmallah, M. Elzeftawi, K. Chang, and P. Hanumolu, “A 6.75to8.25 GHz, 250fsrmsintegratedjitter 3.25 mW rapid on/off PVTinsensitive fractionalN injectionlocked clock multiplier in 65nm CMOS,” IEEE J. SolidState Circuits, vol. 53, pp. 18181829, Jun. 2018. [Link]
 A. Elkholy, S. Saxena, G. Shu, A. Elshazly, and P. Hanumolu, “Lowjitter multioutput alldigital clock generator using DTCbased open loop fractional dividers,” IEEE J. SolidState Circuits, vol. 53, pp. 18061817, Jun. 2018. [Link]
 W.S. Choi, G. Shu, M. Talegaonkar, Y. Liu, D. Wei, L. Benini, and P. Hanumolu, “A 0.450.7V 16Gb/s 0.290.58pJ/b sourcesynchronous transceiver using nearthreshold operation,” IEEE J. SolidState Circuits, vol. 53, no. 3, pp. 884895, Mar. 2018. [Link]
 D. Wei, T. Anand, G. Shu, J. E. SchuttAiné and P. K. Hanumolu, “A 10Gb/s/ch, 0.6pJ/bit/mm power scalable rapidON/OFF transceiver for onchip energy proportional interconnects,” in IEEE J. of SolidState Circuits, pp. 873883, March 2018. [Link]
 S. Kim, W.S. Choi, R. Pilawa, and P. Hanumolu, “A 10MHz 2mA800mA 0.5V1.5V 90% peak efficiency timebased Buck converter with seamless transition between PWM/PFM modes,” IEEE J. SolidState Circuits, vol. 53, no. 3, pp. 814824, Mar. 2018. [Link]
 M. G. Ahmed, M. Talegaonkar, A. Elkholy, G. Shu, A. Elmallah, A. Rylyakov, and P. Hanumolu, “A 12Gb/s 16.8dBm OMA Sensitivity 23mW Optical Receiver in 65nm CMOS,” in IEEE J. of SolidState Circuits, vol. 53, no. 2, pp. 445457, Feb. 2018. [Link]
2017
 M. Talegaonkar, T. Anand, A. Elkholy, A. Elshazly, R. Nandwana, S. Saxena, B. Young, W.S. Choi, and P. Hanumolu, “A 5GHz digital fractionalN PLL using a 1bit deltasigma frequencytodigital converter in 65nm CMOS,” IEEE J. SolidState Circuits, vol. 52, no. 9, pp. 23062320, Sep. 2017. [Link]
 S. Saxena, G. Shu, R. Nandwana, M. Talegaonkar, A. Elkholy, T. Anand, W.S. Choi, and P. Hanumolu, “A 2.8mW/Gb/s 14Gb/s serial link transceiver,” IEEE J. SolidState Circuits, vol. 52, no. 5, pp. 13991411, May. 2017. [Link]
 R. K. Nandwana, S. Saxena, A. Elshazly, K. Mayaram, and P. Hanumolu, “A fullyintegrated low frequency input reference, 1to2048 cascaded digital frequency synthesizer using scrambling TDC, ” IEEE Trans. Circuits Syst. I, vol. 64, pp. 283295, Feb. 2017. [Link]
2016
 R. K. Nandwana, S. Saxena, A. Elshazly, K. Mayaram, and P. K. Hanumolu, “A fullyintegrated low frequency input reference, 1to2048 cascaded digital frequency synthesizer using scrambling TDC,” IEEE Trans. Circuits Syst. I. [Link]
 J. Zhu, R. K. Nandwana, G. Shu, A. Elkholy, S. J. Kim, P. K. Hanumolu, “A 0.0021 mm² 1.82 mW 2.2 GHz PLL using timebased integral control in 65 nm CMOS,” in IEEE J. SolidState Circuits , vol.PP, no.99, pp.113 [Link]
 T. Anand, K. A. A. Makinwa, P. K. Hanumolu, “A VCO based highly digital temperature sensor with 0.034 °C/mV supply sensitivity,” in IEEE J. SolidState Circuits , vol. 51, no. 11, pp. 25612663, Nov. 2016. [Link]
 A. Elkholy, S. Saxena, R. K. Nandwana, A. Elshazly, and P. K. Hanumolu, “A 2.05.5 GHz wide bandwidth ringbased digital fractionalN PLL with extended range multimodulus divider,” in IEEE J. SolidState Circuits, vol. 51, no. 8, pp. 17711784, Aug. 2016. [Link]
 G. Shu, W. S. Choi, S. Saxena, M. Talegaonkar, T. Anand, A. Elkholy, A. Elshazly, and P. K. Hanumolu, “A 4to10.5 Gb/s continuousrate digital clock and data recovery with automatic frequency acquisition,” in IEEE J. SolidState Circuits, vol. 51, no. 2, pp. 428439, Feb. 2016. [Link]
2015

A. Elkholy, M. Talegaonkar, T. Anand, and P. K. Hanumolu, “Design and analysis of lowpower highfrequency robust subharmonic injectionlocked clock multipliers,” IEEE J. SolidState Circuits, vol. 50, no. 12, pp. 31603174, Dec. 2015. [Link]

T. Anand, M. Talegaonkar, A. Elkholy, S. Saxena, A. Elshazly, and P. K. Hanumolu, “A 7 Gb/s embedded clock transceiver for energy proportional links,” IEEE J. SolidState Circuits, vol. 50, no. 12, pp. 31013119, Dec. 2015. [Link]

S.J. Kim, R. K. Nandwana, Q. Khan, R. PilawaPodgurski, and P. K. Hanumolu, “A 4phase 30–70 MHz switching frequency buck converter using a timebased compensator, ” IEEE J. SolidState Circuits, vol. 50, no. 12, pp. 28142824, Dec. 2015. [Link]

P. Prabha, S.J. Kim, K. Reddy, S. Rao, N. Griesert, A. Rao, G. Winter, and P.K. Hanumolu, “A highly digital VCObased ADC architecture for current sensing applications,” IEEE J. SolidState Circuits,vol. 50, no. 8, pp. 17851795, Aug. 2015. [Link]

S.J. Kim, Q. Khan, M. Talegaonkar, A. Elshazly, A. Rao, N. Griesert, G. Winter, W. McIntyre, and P. K. Hanumolu, “High frequency buck converter design using timebased control techniques,” IEEE J. SolidState Circuits,vol. 50, no. 4, pp. 9901001, Apr. 2015. [Link]

R. K. Nandwana, T. Anand, S. Saxena, S. –J. Kim, M. Talegaonkar, A. Elkholy, W.S. Choi, A. Elshazly, and P. K. Hanumolu, “A calibrationfree fractionalN ring PLL using hybrid phase/currentmode phase interpolation method,” IEEE J. SolidState Circuits, vol. 50, no. 4, pp. 882895, Apr. 2015. [Link]

A. Elkholy, T. Anand, W.S. Choi, A. Elshazly, P. K. Hanumolu, “A 3.7mW lownoise widebandwidth 4.5GHz digital fractionalN PLL using time amplifierbased TDC,” IEEE J. SolidState Circuits, vol. 50, no. 4, pp. 867881, Apr. 2015. [Link]

W.S. Choi, T. Anand, G. Shu, A. Elshazly, and P. K. Hanumolu, “A burstmode digital receiver with programmable input jitter filtering for energy proportional links,” IEEE J. SolidState Circuits, vol. 50, no. 3, pp. 237248, Mar. 2015. [Link]
2014

T. Anand, A. Elshazly, M. Talegaonkar, B. Young, and P. Hanumolu, “A 5Gb/s, 10ns powerontime, 36μW offstate power, fast poweron transmitter for energy proportional links”, IEEE J. SolidState Circuits, vol. 49, no 10, pp. 22432258, Oct. 2014. [Link]

M. Talegaonkar, A. Elshazly, K. Reddy, P. Prabha, T. Anand, and P. K. Hanumolu, “An 8 Gb/s–64 Mb/s, 2.3–4.2 mW/Gb/s burstmode transmitter in 90 nm CMOS,” IEEE J. SolidState Circuits, vol. 49, no. 10, pp. 22282242, Oct. 2014. [Link]

S. Saxena, R. K. Nandwana, and P. K. Hanumolu, “A 5Gb/s energyefficient voltagemode transmitter using timebased deemphasis,” IEEE J. SolidState Circuits, vol. 49, no. 8, pp. 18271836, Aug. 2014.[Link]

A. Elshazly, S. Rao, B. Young, and P. Hanumolu, “A noiseshaping timetodigital converter using switchedring oscillators – analysis, design, and measurement techniques,” IEEE J. SolidState Circuits, vol. 49, no. 5, pp. 11841197, May 2014. [Link]

S. Rao, K. Reddy, B. Young, and P. Hanumolu, “A deterministic digital background calibration technique for VCObased ADCs,” IEEE J. SolidState Circuits, vol. 49, no. 4, pp. 950960, Apr. 2014. [Link]

G. Shu, S. Saxena, W. S. Choi, M. Talegaonkar, A. Elshazly, B. Young, and P. K. Hanumolu, “A referenceless clock and data recovery circuit using phaserotating phaselocked loop,” IEEE J. SolidState Circuits, vol. 49, no. 4, pp. 10361047, Apr. 2014. [Link]
2013

A. Elshazly, R. Inti, B. Young, and P.K. Hanumolu, “Clock multiplication techniques using digital multiplying delaylocked loops,” IEEE J. SolidState Circuits, vol. 48, no. 6, pp. 14161428, June 2013.[Link]

R. Zanbaghi, P.K. Hanumolu, and T.S. Fiez, “An 80dB DR, 7.2MHzbandwidth single opamp biquad based CT ΔΣ modulator dissipating 13.7mW,” IEEE J. SolidState Circuits, vol. 48, no. 2, pp. 487501, Feb. 2013. [Link]
2012

K. Reddy, S. Rao, R. Inti, B. Young, A. Elshazly, M. Talegaonkar, and P.K. Hanumolu, “A 16mW 78dB SNDR 10MHz BW CT ΔΣ ADC using residuecancelling VCObased quantizer,” IEEE J. SolidState Circuits, vol. 47, no. 12, pp. 29162927, Dec. 2012. [Link]

B. Drost, M. Talegaonkar, and P.K. Hanumolu, “Analog filter design using ring oscillator integrators,” IEEE J. SolidState Circuits, vol. 47, no. 12, pp. 31203129, Dec. 2012. [Link]

N. Sasidhar, D. Gubbins, P.K. Hanumolu, and U.K. Moon, “Railtorail input pipelined ADC incorporating multistage signal mapping,” IEEE Trans. Circuits Syst. II, vol. 59, no. 9, pp. 558562, Sept. 2012. [Link]

S. Zaliasl, S. Saxena, P.K. Hanumolu, K. Mayaram, and T.S. Fiez, “A 12.5bit 4 MHz 13.8 mW MASH ΔΣ modulator with multirated VCObased ADC,” IEEE Trans. Circuits Syst. I, vol. 59, no. 8, pp. 16041613, Aug. 2012. [Link]
2011

W. Yin, R. Inti, A. Elshazly, M. Talegaonkar, B. Young, and P.K. Hanumolu, “A TDCless 7 mW 2.5 Gb/s digital CDR with linear loop dynamics and offsetfree data recovery,” IEEE J. SolidState Circuits, vol. 46, no. 12, pp. 31633173, Dec. 2011. [Link]

R. Inti, W. Yin, A. Elshazly, N. Sasidhar, and P.K. Hanumolu, “A 0.5to2.5 Gb/s referenceless halfrate digital CDR with unlimited frequency acquisition range and improved input dutycycle error tolerance,” IEEE J. SolidState Circuits, vol. 46, no. 12, pp. 31503162, Dec. 2011. [Link]

S. Rao, Q. Khan, S. Bang, D. Swank, A. Rao, W. McIntyre, and P.K. Hanumolu, “A 1.2A buckboost LED driver with onchip error averaged senseFETbased current sensing technique,” IEEE J. SolidState Circuits, vol. 46, no. 12, pp. 27722783, Dec. 2011. [Link]

A. Elshazly, R. Inti, W. Yin, B. Young, and P.K. Hanumolu, “A 0.4to3GHz digital PLL with PVT insensitive supply noise cancellation using deterministic background calibration,” IEEE J. SolidState Circuits, vol. 46, no. 12, pp. 27592771, Dec. 2011. [Link]

W. Yin, R. Inti, A. Elshazly, B. Young, and P.K. Hanumolu, “A 0.7to3.5 GHz 0.6to2.8 mW highly digital phaselocked loop with bandwidth tracking,” IEEE J. SolidState Circuits, vol. 46, no. 8, pp. 18701880, Aug. 2011. [Link]

Y. Wang, P.K. Hanumolu, and G.C. Temes, “Design techniques for wideband discretetime deltasigma ADCs with extra loop delay,” IEEE Trans. Circuits Syst. I, vol. 58, no. 7, pp. 15181530, July 2011.[Link]

I. Vytyaz, P.K. Hanumolu, U.K. Moon, and K. Mayaram, “Designoriented analysis of circuits with equality constraints,” IEEE Trans. Circuits Syst. I, vol. 58, no. 5, pp. 10891098, May 2011. [Link]
2010

A. Arakali, S. Gondi, and P.K. Hanumolu, “Analysis and design techniques for supplynoise mitigation in phaselocked loops,” IEEE Trans. Circuits Syst. I, vol. 57, no. 11, pp. 28802889, Nov. 2010.[Link]

D. Gubbins, B. Lee, P.K. Hanumolu, and U.K. Moon, “Continuoustime input pipeline ADCs,” IEEE J. SolidState Circuits, vol. 45, no. 8, pp. 14561468, Aug. 2010. [Link]

B. Young, and P.K. Hanumolu, “Phaselocked loop based ΔΣ ADC,” Electronic Letters, vol. 46, no. 6, pp. 403404, Mar. 2010. [Link]
2009

A. Agrawal, A. Liu, P.K. Hanumolu, and G.Y. Wei, “An 8×5 Gb/s parallel receiver with collaborative timing recovery,” IEEE J. SolidState Circuits, vol. 44, no. 11, pp. 31203130, Nov. 2009. [Link]

N. Sasidhar, Y.J. Kook, S. Takeuchi, K. Hamashita, K. Takasuka, P.K. Hanumolu, and U.K. Moon, “A low power pipelined ADC using capacitor and opamp sharing technique with a scheme to cancel the effect of signal dependent kickback,” IEEE J. SolidState Circuits, vol. 44, no. 9, pp. 23922401, Sept. 2009. [Link]

M.G. Kim, P.K. Hanumolu, and U.K. Moon, “A 10 MS/s 11bit 0.19 mm^{2} algorithmic ADC with improved clocking scheme,” IEEE J. SolidState Circuits, vol. 44, no. 9, pp. 23482355, Sept. 2009. [Link]

A. Arakali, S. Gondi, and P.K. Hanumolu, “Lowpower supplyregulation techniques for ring oscillators in phaselocked loops using a splittuned architecture,” IEEE J. SolidState Circuits, vol. 44, no. 8, pp. 21692181, Aug. 2009. [Link]

N. Sasidhar, R. Inti, and P.K. Hanumolu, “Lownoise selfreferenced cmos oscillator,” Electronics Letters, vol. 45, no. 18, pp. 920921, Aug. 2009. [Link]

V. Kratyuk, P.K. Hanumolu, K. Ok, U.K. Moon, and K. Mayaram, “A digital PLL with a stochastic timetodigital converter,” IEEE Trans. Circuits Syst. I, vol. 56, no. 8, pp. 16121621, Aug. 2009. [Link]

I. Vytyaz, D.C. Lee, P.K. Hanumolu, U.K. Moon, and K. Mayaram, “Automated design and optimization of lownoise oscillators,” IEEE Trans. ComputerAided Design of Integr. Circuits Syst., vol. 28, no. 5, pp. 609622, May 2009. [Link]

T. Wu, P.K. Hanumolu, K. Mayaram, and U.K. Moon, “Method for a constant loop bandwidth in LCVCO PLL frequency synthesizers,” IEEE J. SolidState Circuits, vol. 44, no. 2, pp. 427435, Feb. 2009. [Link]
2008

I. Vytyaz, D.C. Lee, P.K. Hanumolu, U.K. Moon, and K. Mayaram, “Sensitivity analysis for oscillators,” IEEE Trans. ComputerAided Design of Integr. Circuits Syst., vol. 27, no. 9, pp. 15211534, Sept. 2008. [Link]

M.G. Kim, G.C. Ahn, P.K. Hanumolu, S.H. Lee, S.H. Kim, S.B. You, J.W. Kim, G.C. Temes, and U.K. Moon, “A 0.9V 92dB doublesampled switchedRC deltasigma audio ADC,” IEEE J. SolidState Circuits, vol. 43, no. 5, pp. 11951206, May 2008. [Link]

P.K. Hanumolu, G.Y. Wei, and U.K. Moon, “A widetracking range clock and data recovery circuit,” IEEE J. SolidState Circuits, vol. 43, no. 2, pp. 425439, Feb. 2008. [Link]

P.K. Hanumolu, V. Kratyuk, G.Y. Wei, and U.K. Moon, “A subpicosecond resolution 0.51.5 GHz digitaltophase converter,” IEEE J. SolidState Circuits, vol. 43, no. 2, pp. 414424, Feb. 2008. [Link]
2007

P. Kurahashi, P.K. Hanumolu, G.C. Temes, and U.K. Moon, “Design of lowvoltage highly linear switchedRMOSFETC filters,” IEEE J. SolidState Circuits, vol. 42, no. 8, pp. 16991709, Aug. 2007. [Link]

V. Kratyuk, P.K. Hanumolu, U.K. Moon, and K. Mayaram, “A design procedure for alldigital phaselocked loops based on a chargepump phaselockedloop analogy,” IEEE Trans. Circuits Syst. II, vol. 54, no. 3, pp. 247251, Mar. 2007. [Link]

V. Kratyuk, P.K. Hanumolu, U.K. Moon, and K. Mayaram, “Frequency detector for fast frequency lock of digital PLLs,” Electronics Letters, vol. 43, no. 1, pp. 1314, Jan. 2007. [Link]
2006

M. Brownlee, P.K. Hanumolu, K. Mayaram, and U.K. Moon, “A 0.5GHz to 2.5GHz PLL with fully differential supply regulated tuning,” IEEE J. SolidState Circuits, vol. 41, no. 12, pp. 27202728, Dec. 2006. [Link]
2005

G. Vemulapalli, P.K. Hanumolu, Y.J. Kook, and U.K. Moon, “A 0.8V accurately tuned linear continuoustime filter,” IEEE J. SolidState Circuits, vol. 40, no. 9, pp. 19721977, Sept. 2005. [Link]
2004

P.K. Hanumolu, M. Brownlee, K. Mayaram, and U.K. Moon, “Analysis of chargepump phaselocked loops,” IEEE Trans. Circuits Syst. I, vol. 51, no. 9, pp. 16651674, Sept. 2004. [Link]
Conference [Back to Top]
2018
 D. Kim, W. Choi, A. Elkholy, J. Kenney, P. Hanumolu, “A 15Gb/s 1.9pJ/bit subbaudrate digital CDR,” in IEEE Custom Int. Circuits Conf., Apr. 2018. [Link]
 A. Elmallah, M. Ahmed, A. Elkholy, W.S. Choi, P. Hanumolu, “A 1.6ps peakINL 5.3ns range twostep digitaltotime converter in 65nm CMOS,” in IEEE Custom Int. Circuits Conf., Apr. 2018. [Link]
 K. Megawer, A. Elkholy, D. Coombs, M. Ahmed, A. Elmallah, P. Hanumolu, “A 5GHz 370fs rms 6.5mW clock multiplier using a crystaloscillator frequency quadrupler in 65nm CMOS,” in ISSCC Digest of Technical Papers, Feb. 2018, pp. 392393. [Link]
2017
 B. Salz, M. Talegaonkar, G. Shu, A. Elmallah, R. Nandwana, B. Sahoo, P. Hanumolu, “A 0.7V Timebased Inductor for Fully Integrated Low Bandwidth Filter Applications,” in IEEE Custom Int. Circuits Conf., May 2017. [Link]
 S. J. Kim, W. Choi, R. Pilawa Podgurski, P. Hanumolu, “A 10MHz 2mA800mA 0.5V1.5V 90% peak efficiency timebased buck converter with seamless transition between PWM/PFM modes,” in IEEE Custom Int. Circuits Conf., May 2017. [Link]
 J. Zhu, M. Mahalley, G. Shu, W.S. Choi, R.K. Nandwana, A. Elkholy, B. Sahoo, P. Hanumolu, “A 4575MHz 197452mW oscillator with 164.6dB FoM and 2.3psrms period jitter in 65nm CMOS,” in IEEE Custom Int. Circuits Conf., May 2017. [Link]
 R. K. Nandwana, S. Saxena, A. Elkholy, M. Talegaonkar, J. Zhu, WS. Choi, A. Elmallah, P.Hanumolu, “A 3to10Gb/s 5.75pJ/b transceiver with flexible clocking in 65nm CMOS,” in ISSCC Digest of Technical Papers, Feb. 2017, pp. 492493. [Link]
 WC. Liu, P. Assem, Y. Lei, P. Hanumolu, R. PilawaPodgurski, “A 94.2%PeakEfficiency 1.53A Directbatteryhookup hybrid Dickson switchedcapacitor DCDC converter with wide continuous conversion ratio in 65nm CMOS,” in ISSCC Digest of Technical Papers, Feb. 2017, pp.182183. [Link]
 D. Coombs, A. Elkholy, R. K. Nandwana, A. Elmallah, P. Hanumolu, “A 2.5to5.75GHz 5mW 0.3psrmsjitter cascaded ringbased digital injectionlocked clock multiplier in 65nm CMOS,” in ISSCC Digest of Technical Papers, Feb. 2017, pp. 152153. [Link]
2016
 J. Zhu, R. K. Nandwana, G. Shu, A. Elkholy, S. J. Kim and P. K. Hanumolu, “19.8 A 0.0021mm2 1.82mW 2.2GHz PLL using timebased integral control in 65nm CMOS,” 2016 IEEE International SolidState Circuits Conference (ISSCC), San Francisco, CA, 2016, pp. 338340. [Link]
 A. Elkholy, A. Elmallah, M. Elzeftawi, K. Chang and P. K. Hanumolu, “10.6 A 6.75to8.25GHz, 250fsrmsintegratedjitter 3.25mW rapid on/off PVTinsensitive fractionalN injectionlocked clock multiplier in 65nm CMOS,” 2016 IEEE International SolidState Circuits Conference (ISSCC), San Francisco, CA, 2016, pp. 192193. [Link]
 G. Shu et al., “23.1 A 16Mb/sto8Gb/s 14.1to5.9pJ/b source synchronous transceiver using DVFS and rapid on/off in 65nm CMOS,” 2016 IEEE International SolidState Circuits Conference (ISSCC), San Francisco, CA, 2016, pp. 398399. [Link]
2015

A. Elkholy, S. Saxena, R. K. Nandwana, A. Elshazly, and P. K. Hanumolu, “A 4mW wide bandwidth ringbased fractionalN DPLL with 1.9psrms integrated jitter,” in Proc. IEEE Custom Integr. Circuits Conf. (CICC), Sep. 2015. [Link]

S. Saxena, G. Shu, R. K. Nandwana, M. Talegaonkar, A. Elkholy, T. Anand, S. J. Kim, W.–S. Choi, and P. K. Hanumolu, “A 2.8mW/Gb/s 14Gb/s serial link transceiver in 65nm CMOS,” in IEEE Symp. VLSI Circuits, Jun. 2015. [Link]

T. Anand, K.A.A. Makinwa, P. K. Hanumolu , “A selfreferenced VCObased temperature sensor with 0.034°C/mV supply sensitivity in 65nm CMOS,” in IEEE Symp. VLSI Circuits, Jun. 2015. [Link]

A. Elkholy, M. Talegaonkar, T. Anand, P. K. Hanumolu, “A 6.758.25GHz 2.25mW 190fsrms IntegratedJitter PVTinsensitive InjectionLocked Clock Multiplier Using AllDigital Continuous Frequency Tracking Loop in 65nm CMOS”, in IEEE ISSCC Dig. Tech. Papers, Feb. 2015. [Link]

S.J. Kim, R. K. Nandwana, Q. Khan, R. Pilawa, P. K. Hanumolu, “A 1.8V 30to70MHz 87% PeakEfficiency 0.32mm2 4Phase TimeBased Buck Converter Consuming 3µA/MHz Quiescent Current in 65nm CMOS”, in IEEE ISSCC Dig. Tech. Papers, Feb. 2015. [Link]

W.S. Choi, G. Shu, M. Talegaonkar, Y. Liu, D. Wei, L. Benini and P. Hanumolu, “A 0.45to0.7V 1to6Gb/s 0.29to0.58pJ/b sourcesynchronous transceiver using automatic phase calibration in 65nm CMOS”, in IEEE ISSCC Dig. Tech. Papers, Feb. 2015. [Link]

T. Anand, M. Talegaonkar, A. Elkholy, S. Saxena, A. Elshazly, and P. Hanumolu, “A 7Gb/s rapid on/off embedded clock serial link transceiver with 20ns poweron time, 740μW offstate power for energy proportional links in 65nm CMOS”, in IEEE ISSCC Dig. Tech. Papers, Feb. 2015. [Link]
2014

P. Prabha, S. –J. Kim, K. Reddy, S. Rao, N. Griesert, A. Rao, G. Winter, and P. K. Hanumolu, “A VCObased currenttodigital converter for sensor applications,” in IEEE Custom Int. Circuits Conf., Sep. 2014. [Link]

Q. Khan, S. Kim, M. Talegaonkar, A. Elshazly, A. Rao, N. Griesert, G. Winter, W. McIntyre, and P. Hanumolu, “A 1025MHz, 600mA buck converter using timebased PID compensator with 2μA/MHz quiescent current, 94% peak efficiency, and 1MHz BW” in IEEE Symp. VLSI Circuits, Jun. 2014. [Link]

R. Nandwana, T. Anand, S. Saxena, S. Kim, M. Talegaonkar, A. Elkholy, W. Choi, A. Elshazly, and P. Hanumolu, “4.25GHz4.75GHz calibrationfree fractionalN ring PLL using hybrid phase/currentmode phase interpolator with 13.2dB phase noise improvement,” in IEEE Symp. VLSI Circuits, Jun. 2014. [Link]

B. Young, K. Reddy, S. Rao, A. Elshazly, T. Anand, and P. Hanumolu, “A 75dB DR 50MHz BW 3rd order CTΔΣ modulator using VCObased integrators,” in IEEE Symp. VLSI Circuits, Jun. 2014. [Link]

M. Talegaonkar, T. Anand, A. Elkholy, A. Elshazly, R. Nandwana, S. Saxena, B. Young, W. Choi, P. Hanumolu, “A 4.45.4GHz digital fractionalN PLL using ΔΣ frequencytodigital converter,” in IEEE Symp. VLSI Circuits, Jun. 2014. [Link]

A. Elkholy, T. Anand, W. Choi, A. Elshazly, and P. Hanumolu, “A 3.7mW 3MHz bandwidth 4.5GHz digital fractionalN PLL with106dBc/Hz inband noise using time amplifier based TDC,” in IEEE Symp. VLSI Circuits, Jun. 2014. [Link]

A. Elkholy, A. Elshazly, S. Saxena, G. Shu, and P. Hanumolu, “A 20to1000MHz ±14ps peaktopeak jitter reconfigurable multioutput alldigital clock generator using openloop fractional dividers in 65nm CMOS,” in ISSCC Digest of Technical Papers, Feb. 2014. [Link]

G. Shu, W. Choi, S. Saxena, T. Anand, A. Elshazly, and P. Hanumolu, “A 4to10.5Gb/s 2.2mW/Gb/s continuousrate digital CDR with automatic frequency acquisition in 65nm CMOS,” in ISSCC Digest of Technical Papers, Feb. 2014. [Link]
2013

S. Saxena, R. Nandwana, P. Hanumolu, “A 5 Gb/s 3.2 mW/Gb/s 28 dB losscompensating pulsewidth modulated voltagemode transmitter,” in IEEE Custom Int. Circuits Conf., Sep. 2013. [Link]

W. Choi, T. Anand, G. Shu, and P. Hanumolu, “A fast poweron 2.2Gb/s burstmode digital CDR with programmable input jitter filtering,” in IEEE Symp. VLSI Circuits, Jun. 2013. [Link]

G. Shu, S. Saxena, W. Choi, M. Talegaonkar, R. Inti, A. Elshazly, B. Young, and P. Hanumolu, “A 5Gb/s 2.6mW/Gb/s referenceless halfrate PRPLLbased digital CDR,” in IEEE Symp. VLSI Circuits, Jun. 2013. [Link]

S. Rao, K. Reddy, B. Young, and P. Hanumolu, “A 4.1mW, 12bit ENOB, 5MHz BW, VCObased ADC with onChip deterministic digital background calibration in 90nm CMOS,” in IEEE Symp. VLSI Circuits, Jun. 2013. [Link]

R. Nandwana, S. Saxena, A. Elshazly, K. Mayaram, and P. Hanumolu, “A 2.5GHz 5.4mW 1to2048 digital clock multiplier using a scrambling TDC,” in IEEE Symp. VLSI Circuits, Jun. 2013. [Link]

T. Anand, M. Talegaonkar, A. Elshazly, B. Young, and P. Hanumolu, “A 2.5GHz, 2.2mW/25µW On/Offstate power, 2psrms longterm jitter, digital clock multiplier with 3 reference cycles poweron time,” in ISSCC Digest of Technical Papers, Feb. 2013. [Link]
2012

A. Elshazly, R. Inti, M. Talegaonkar, and P.K. Hanumolu, “A 1.5GHz 1.35mW 112dBc/Hz inband noise digital phaselocked loop with 50fs/mV supplynoise sensitivity,” in Proc. Symposium on VLSI Circuits (VLSIC), June 2012, pp. 188189. [Link]

Q. Khan, A. Elshazly, S. Rao, R. Inti, and P.K. Hanumolu, “A 900mA 93% efficient 50µA quiescent current fixed frequency hysteretic buck converter using a highly digital hybrid voltage and currentmode control,” in Proc. Symposium on VLSI Circuits (VLSIC), June 2012, pp. 182183. [Link]

T. Tong, W. Yu, P.K. Hanumolu, and G.C. Temes, “Calibration technique for SAR analogtodigital converters,” in IEEE Intl. Symp. on Circuits and Systems, May 2012, pp. 29932996. [Link]

A. Elshazly, S. Rao, B. Young, and P.K. Hanumolu, “A 13b 315fs_{rms}2mW 500MS/s 1MHz bandwidth highly digital timetodigital converter using switched ring oscillators,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2012, pp. 464466. [Link]

B. Drost, M. Talegaonkar, and P.K. Hanumolu, “A 0.55V 61dBSNR 67dBSFDR 7MHz 4^{th}order Butterworth filter using ringoscillatorbased integrators in 90nm CMOS,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2012, pp. 360362. [Link]

A. Elshazly, R. Inti, B. Young, and P.K. Hanumolu, “A 1.5GHz 890μW digital MDLL with 400fs_{rms} integrated jitter, 55.6dBc reference spur and 20fs/mV supplynoise sensitivity using 1b TDC,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2012, pp. 242244. [Link]

K. Reddy, S. Rao, R. Inti, B. Young, A. Elshazly, M. Talegaonkar, and P.K. Hanumolu, “A 16mW 78dBSNDR 10MHzBW CTΔΣ ADC using residuecancelling VCObased quantizer,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2012, pp. 152154. [Link]
2011

A. Agrawal, P.K. Hanumolu, and G.Y. Wei, “Area efficient phase calibration of a 1.6 GHz multiphase DLL,” in IEEE Custom Integrated Circuits Conference (CICC), Sept. 2011, pp. 14. [Link]

B. Yang, B. Drost, S. Rao, and P.K. Hanumolu, “A highPSR LDO using a feedforward supplynoise cancellation technique,” in IEEE Custom Integrated Circuits Conference (CICC), Sept. 2011, pp. 14. [Link]

S. Lee, J. Chae, M. Aniya, S. Takeuchi, K. Hamashita, P.K. Hanumolu, and G.C. Temes, “A doublesampled lowdistortion cascade ΔΣ modulator with an adder/integrator for WLAN application,” in IEEE Custom Integrated Circuits Conference (CICC), Sept. 2011, pp. 14.[Link]

M. Talegaonkar, R. Inti, and P.K. Hanumolu, “Digital clock and data recovery circuit design: Challenges and tradeoffs,” in IEEE Custom Integrated Circuits Conference (CICC), Sept. 2011, pp. 18. [Link]

S. Zaliasl, S. Saxena, P.K. Hanumolu, K. Mayaram, and T.S. Fiez, “A 77dB SNDR, 4MHz MASH ΔΣ modulator with a secondstage multirate VCObased quantizer,” in IEEE Custom Integrated Circuits Conference (CICC), Sept. 2011, pp. 14. [Link]

Q. Khan, S. Rao, D. Swank, A. Rao, W. McIntyre, S. Bang, and P.K. Hanumolu, “A 3.3V 500mA digital BuckBoost converter with 92% peak efficiency using constant ON/OFF time deltasigma fractionalN control,” in Proc. IEEE Euro. SolidState Circuits Conference (ESSCIRC), Sept. 2011, pp. 439442. [Link]

S. Rao, B. Young, A. Elshazly, W. Yin, N. Sasidhar, and P.K. Hanumolu, “A 71dB SFDR open loop VCObased ADC using 2level PWM modulation,” in Proc. Symposium on VLSI Circuits (VLSIC), June 2011, pp. 270271. [Link]

W. Yin, R. Inti, A. Elshazly, and P.K. Hanumolu, “A TDCless 7mW 2.5Gb/s digital CDR with linear loop dynamics and offsetfree data recovery,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2011, pp. 440442.[Link]

R. Inti, W. Yin, A. Elshazly, N. Sasidhar, and P.K. Hanumolu, “A 0.5to2.5Gb/s referenceless halfrate digital CDR with unlimited frequency acquisition range and improved input dutycycle error tolerance,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2011, pp. 438450.[Link]

S. Rao, Q. Khan, S. Bang, D. Swank, A. Rao, W. McIntyre, and P.K. Hanumolu, “A 1.2A buckboost LED driver with 13% efficiency improvement using erroraveraged SenseFETbased current sensing,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2011, pp. 238240. [Link]

R. Inti, A. Elshazly, B. Young, W. Yin, M. Kossel, T. Toifl, and P.K. Hanumolu, “A highly digital 0.5to4Gb/s 1.9mW/Gb/s seriallink transceiver using currentrecycling in 90nm CMOS,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2011, pp. 152154. [Link]

A. Elshazly, R. Inti, W. Yin, B. Young, and P.K. Hanumolu, “A 0.4to3GHz digital PLL with supplynoise cancellation using deterministic background calibration,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2011, pp. 9294. [Link]
2010

W. Yin, R. Inti, and P.K. Hanumolu, “A 1.6mW 1.6psrmsjitter 2.5GHz digital PLL with 0.7to3.5GHz frequency range in 90nm CMOS,” in IEEE Custom Integrated Circuits Conference (CICC), Sept. 2010, pp. 14. [Link]

B. Young, S. Kwon, A. Elshazly, and P.K. Hanumolu, “A 2.4ps resolution 2.1mW secondorder noiseshaped timetodigital converter with 3.2ns range in 1MHz bandwidth,” in IEEE Custom Integrated Circuits Conference (CICC), Sept. 2010, pp. 14. [Link]

S. Bang, D. Swank, A. Rao, W. McIntyre, Q. Khan, and P.K. Hanumolu, “A 1.2A 2MHz trimode BuckBoost LED driver with feedforward duty cycle correction,” in IEEE Custom Integrated Circuits Conference (CICC), Sept. 2010, pp. 14. [Link]

J. Chae, S. Lee, M. Aniya, S. Takeuchi, K. Hamashita, P.K. Hanumolu, and G.C. Temes, “A 63 dB 16 mW 20 MHz BW doublesampled ΔΣ analogtodigital converter with an embeddedadder quantizer,” in IEEE Custom Integrated Circuits Conference (CICC), Sept. 2010, pp. 14. [Link]
2009

S. Weaver, B. Hershberg, P.K. Hanumolu, and U.K. Moon, “A multiplexerbased digital passive linear counter (PLINCO),” in Proc. IEEE Intl. Conf. on Electronics, Circuits and Systems (ICECS), Dec. 2009, pp. 607610. [Link]

D. Gubbins, S. Kwon, B. Lee, P.K. Hanumolu, and U.K. Moon, “A continuoustime input pipeline ADC with inherent antialias filtering,” in Proc. IEEE Custom Integrated Circuits Conference (CICC), Sept. 2009, pp. 275278. [Link]

S. Kwon, P.K. Hanumolu, S.H. Kim, S.N. Lee, S.B. You, H.J. Park, J.W. Kim, and U.K. Moon, “An 11mW 100MHz 16XOSR 64dBSNDR hybrid CT/DT ΔΣ ADC with relaxed DEM timing,” in Proc. IEEE Custom Integrated Circuits Conference (CICC), Sept. 2009, pp. 171174.[Link]

O. Rajaee, T. Musah, S. Takeuchi, M. Aniya, K. Hamashita, P.K. Hanumolu, and U.K. Moon, “A 79dB 80 MHz 8XOSR hybrid deltasigma/pipeline ADC,” in Proc. Symposium on VLSI Circuits (VLSIC), June 2009, pp. 7475. [Link]
2008

M.G. Kim, V. Kratyuk, P.K. Hanumolu, G.C. Ahn, S. Kwon, and U.K. Moon, “An 8mW 10b 50MS/s pipelined ADC using 25dB opamp,” in Proc. IEEE Asian SolidState Circuits Conference (ASSCC), Nov. 2008, pp. 4952. [Link]

A. Arakali, N. Talebbeydokthi, S. Gondi, and P.K. Hanumolu, “Supplynoise mitigation techniques in phaselocked loops,” in Proc. IEEE Euro. SolidState Circuits Conference (ESSCIRC), Sept. 2008, pp. 374377. [Link]

P. Kurahashi, P.K. Hanumolu, and U.K. Moon, “A 1V downconversion filter using dutycycle controlled bandwidth tuning,” in Proc. IEEE Custom Integrated Circuits Conference (CICC), Sept. 2008, pp. 707710. [Link]

I. Vytyaz, J. Carnes, T. Wu, P.K. Hanumolu, U.K. Moon, and K. Mayaram, “Noise tolerant oscillator design using perturbation projection vector analysis,” in Proc. IEEE Custom Integrated Circuits Conference (CICC), Sept. 2008, pp. 695698. [Link]

A. Agrawal, P.K. Hanumolu, and G.Y. Wei, “A 8x—5 Gb/s sourcesynchronous receiver with clock generator phase error correction,” in Proc. IEEE Custom Integrated Circuits Conference (CICC), Sept. 2008, pp. 459462. [Link]

A. Arakali, S. Gondi, and P.K. Hanumolu, “A 0.5to2.5GHz supplyregulated PLL with noise sensitivity of 28dB,” in Proc. IEEE Custom Integrated Circuits Conference (CICC), Sept. 2008, pp. 443446.[Link]

D. Gubbins, B. Lee, P.K. Hanumolu, and U.K. Moon, “A continuoustime input pipeline ADC,” in Proc. IEEE Custom Integrated Circuits Conference (CICC), Sept. 2008, pp. 169172. [Link]

I. Vytyaz, P.K. Hanumolu, U.K. Moon, and K. Mayaram, “Periodic SteadyState Analysis Augmented with Design Equality Constraints,” in Proc. Design, Automation and Test in Europe (DATE), March 2008, pp. 312317. [Link]

A. Agrawal, P.K. Hanumolu, and G.Y. Wei, “An 8x—3.2Gb/s Parallel Receiver with Collaborative Timing Recovery,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2008, pp. 468628. [Link]
2007

J. Carnes, I. Vytyaz, P.K. Hanumolu, K. Mayaram, and U.K. Moon, “Design and Analysis of Noise Tolerant Ring Oscillators Using Maneatis Delay Cells,” in Proc. IEEE Intl. Conf. on Electronics, Circuits and Systems (ICECS), Dec. 2007, pp. 494497. [Link]

N. Sasidhar, Y.J. Kook, S. Takeuchi, K. Hamashita, K. Takasuka, P.K. Hanumolu, and U.K. Moon, “A 1.8V 36mW 11bit 80MS/s pipelined ADC using capacitor and opamp sharing,” in Proc. IEEE Asian SolidState Circuits Conference (ASSCC), Nov. 2007, pp. 240243. [Link]

I. Vytyaz, D.C. Lee, P.K. Hanumolu, U.K. Moon, and K. Mayaram, “Sensitivity analysis for oscillators,” in Proc. IEEE/ACM Intl. Conf. on ComputerAided Design (ICCAD), Nov. 2007, pp. 458463. [Link]

T. Wu, P.K. Hanumolu, K. Mayaram, and U.K. Moon, “A 4.2 GHz PLL frequency synthesizer with an adaptively tuned coarse loop,” in Proc. IEEE Custom Integrated Circuits Conference (CICC), Sept. 2007, pp. 547550. [Link]

P.K. Hanumolu, G.Y. Wei, U.K. Moon, and K. Mayaram, “Digitallyenhanced phaselocking circuits,” in Proc. IEEE Custom Integrated Circuits Conference (CICC), Sept. 2007, pp. 361368. [Link]

M. Brownlee, P.K. Hanumolu, and U.K. Moon, “A 3.2Gb/s oversampling CDR with improved jitter tolerance,” in Proc. IEEE Custom Integrated Circuits Conference (CICC), Sept. 2007, pp. 353356. [Link]

G.C. Ahn, M.G. Kim, P.K. Hanumolu, and U.K. Moon, “A 1V 10b 30MSPS switchedRC pipelined ADC,” in Proc. IEEE Custom Integrated Circuits Conference (CICC), Sept. 2007, pp. 325328. [Link]

V. Kratyuk, P.K. Hanumolu, K. Mayaram, and U.K. Moon, “A 0.6GHz to 2GHz digital PLL with wide tracking range,” in Proc. IEEE Custom Integrated Circuits Conference (CICC), Sept. 2007, pp. 305308.[Link]
2006

P. Kurahashi, P.K. Hanumolu, G. Temes, and U.K. Moon, “A 0.6V highly linear switchedRMOSFETC filter,” in Proc. IEEE Custom Integrated Circuits Conference (CICC), Sept. 2006, pp. 833836.[Link]

P.K. Hanumolu, M.G. Kim, G.Y. Wei, and U.K. Moon, “A 1.6Gbps digital clock and data recovery circuit,” in Proc. IEEE Custom Integrated Circuits Conference (CICC), Sept. 2006, pp. 603606.[Link]

G.C. Ahn, P.K. Hanumolu, M. Kim, S. Takeuchi, T. Sugimoto, K. Hamashita, K. Takasuka, G. Temes, and U.K. Moon, “A 12b 10MS/s Pipelined ADC using reference scaling,” in Proc. Symposium on VLSI Circuits (VLSIC), June 2006, pp. 220221. [Link]

M.G. Kim, G.C. Ahn, P.K. Hanumolu, S.H. Lee, S.H. Kim, S.B. You, J.W. Kim, G.C. Temes, and U.K. Moon, “A 0.9V 92dB doublesampled switchedRC SD audio ADC,” in Proc. Symposium on VLSI Circuits (VLSIC), June 2006, pp. 160161. [Link]

P.K. Hanumolu, V. Kratyuk, G.Y. Wei, and U.K. Moon, “A Subpicosecond resolution 0.51.5GHz digitaltophase converter,” in Proc. Symposium on VLSI Circuits (VLSIC), June 2006, pp. 7576. [Link]

P.K. Hanumolu, G.Y. Wei, and U.K. Moon, “A wide tracking range 0.24Gbps clock and data recovery circuit,” in Proc. Symposium on VLSI Circuits (VLSIC), June 2006, pp. 7172. [Link]

M.G. Kim, P.K. Hanumolu, and U.K. Moon, “A 10MS/s 11b 0.19mm^{2}algorithmic ADC with improved clocking,” in Proc. Symposium on VLSI Circuits (VLSIC), June 2006, pp. 4950. [Link]

V. Kratyuk, P.K. Hanumolu, K. Ok, K. Mayaram, and U.K. Moon, “A digital PLL with a stochastic timetodigital converter,” in Proc. Symposium on VLSI Circuits (VLSIC), June 2006, pp. 3132. [Link]

N. Talebbeydokhti, P.K. Hanumolu, P. Kurahashi, and U.K. Moon, “Constant transconductance bias circuit with an onchip resistor,” in IEEE Intl. Symp. on Circuits and Systems (ISCAS), May 2006, pp. 28572860. [Link]

M. Brownlee, P.K. Hanumolu, K. Mayaram, and U.K. Moon, “A 0.5 to 2.5GHz PLL with fully differential supplyregulated tuning,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2006, pp. 24122421. [Link]
2005

T. Wu, P.K. Hanumolu, U.K. Moon, and K. Mayaram, “An FMDLL based dualloop frequency synthesizer for 5 GHz WLAN applications,” in IEEE Intl. Symp. on Circuits and Systems (ISCAS), May 2005, vol. 4, pp. 39863989. [Link]

V. Kratyuk, P.K. Hanumolu, U.K. Moon, and K. Mayaram, “A low spur fractionalN frequency synthesizer architecture,” in IEEE Intl. Symp. on Circuits and Systems(ISCAS), May 2005, vol. 3, pp. 28072810.[Link]
2004

M. Brownlee, P.K. Hanumolu, U.K. Moon, and K. Mayaram, “The effect of power supply noise on ring oscillator phase noise,” in Proc. IEEE Northeast Workshop on Circuits and Systems (NEWCAS), June 2004, pp. 225228. [Link]

P.K. Hanumolu, B. Casper, R. Mooney, G.Y. Wei, and U.K. Moon, “Jitter in highspeed serial and parallel links,” in IEEE Intl. Symp. on Circuits and Systems (ISCAS), May 2004, vol. 4, pp. 425428. [Link]

G. Vemulapalli, P.K. Hanumolu, and U.K. Moon, “A 0.8V accuratelytuned continuoustime filter,” in Proc. IEEE Custom Integrated Circuits Conference (CICC), Oct. 2004, pp. 4548. [Link]